Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
A design for instantiation in programmable logic or in hardwired logic may be provided as a “netlist.” With respect to programmable logic, conventionally what is known as a “core” is provided as a code listing from which a “netlist” may be generated for providing a configuration bitstream for configuring such programmable logic, such as programmable logic of an FPGA for example. Because cores are often instantiated in multiple applications by different users, cores tend to be associated with circuits that are commonly used. Examples of core circuits are a Reed-Solomon (“RS”) encoder core and an RS decoder core. Notably, encoding and decoding cores may be combined to provide what is known as a “CODEC”; however, encoding and decoding cores may be provided as separate circuit blocks. Even though an example of a core is used herein, it should be understood use of the term “core” is meant to include a design for instantiation in either programmable logic or non-programmable logic, or a combination thereof.
RS codes are used to encode and decode data in many known digital applications, including forward error correction (“FEC”) in communications systems. Generally, R check symbols are appended to K data symbols by an RS encoder prior to data transmission. This allows an RS decoder on a receiving end of the data transmission to correct up to R/2 symbol errors within a symbol code block of N symbols, namely where N equals K plus R. Hence, an RS code is a type of a code known generally as a block code.
An erasure, e, is a symbol in encoded data that a decoder determines has a reasonably high likelihood of containing one or more errors. For an RS decoder configured to handle erasures, the number of errors that may be corrected, E, is determined from Equation 1 below, where e is the number of erasures flagged or otherwise identified:2E+e≦R.  (1)Some RS decoders have an erasure input port to receive an asserted erasure signal responsive to an erased symbol being sampled from data input.
Known communication standards use variable length block codes, namely codes with variable block lengths. These variable length block codes may further have a variable number of check symbols, while using the same generator polynomial, g(x), as generally indicated below in Equation 2:
                              g          ⁡                      (            x            )                          =                              ∏                          i              =              0                                      R              -              1                                ⁢                                          ⁢                                    (                              x                -                                  α                                      hx                    ⁡                                          (                                              Generator_Start                        ⁢                                                                                                  +                        i                                            )                                                                                  )                        .                                              (        2        )            Notably, the type of variable length block codes for these purposes is where the number of check symbols is varied by not transmitting some of them. For purposes of clarity by way of example and not limitation, an IEEE 802.16d communications standard allows blocks of length 124, 120, 116, or 112 with 16, 12, 8, or 4 check symbols respectively. An RS decoder configured to handle such a variable number of check symbols heretofore has generally led to significantly more circuitry than an RS decoder that is configured to handle a single fixed number of check symbols.
Accordingly, it would be desirable and useful to provide means to handle a variable number of check symbols, such as for RS decoding, with less circuitry than was previously used.